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Fortunately, I have a trick up my sleeve. Decades ago, I designed a CPU architecture called “ADAM” for my PhD thesis. Most of the details are irrelevant except for one trick: instead of putting only registers in the register file, I map a portion of them to queues, causing them to take on full/empty blocking semantics at the architectural level. This trick enables a lot of things, from lightweight instruction-level parallelism to enabling fast, low-latency communication between processors and I/O resources. It is the latter property we use here.